An integrated circuit may include a metal oxide semiconductor (MOS) transistor with epitaxial source/drain regions. For example, a p-channel metal oxide semiconductor (PMOS) transistor may have silicon-germanium epitaxial source/drain regions. An n-channel metal oxide semiconductor (NMOS) transistor may have phosphorus-doped silicon epitaxial source/drain regions. An instance of the epitaxial source/drain regions may abut field oxide formed by a shallow trench isolation (STI) process. The epitaxial source/drain region may have a highly angled surface facet and a cavity between the epitaxial material and the dielectric material of the field oxide.
A gate structure may be located on the field oxide adjacent to the epitaxial source/drain region so that dielectric spacer material on a lateral surface of the gate structure may extend into the cavity and down to the epitaxial material, reducing an area for metal silicide on the epitaxial source/drain region. A contact disposed on the epitaxial source/drain region may undesirably provide a high resistance connection to the MOS transistor due to the reduced silicide area and possibly in combination with alignment tolerance of the contact to the source/drain region.